This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-267676, filed Sep. 4, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having trench type device isolation regions and a method of manufacturing the semiconductor device. More specifically, the present invention relates to the structure of trench type device isolation regions of a semiconductor device having semiconductor active regions self-aligned to electrode layers and a method of formation thereof. The present invention is applied, for example, to a nonvolatile memory having a two-layer (stacked) gate structure in which the floating gate is self-aligned to a device isolation region.
2. Description of the Related Art
As a nonvolatile semiconductor storage device that is electrically re-programmable which is adapted for high packing density and large capacity, a flash memory is well known. The flash memory has an array of memory cells of the MOS transistor structure in which two gate electrode layers are stacked; a charge storage layer (floating gate electrode) and a control gate electrode layer.
In the memory cell array of a NAND type flash memory, a plurality of memory cells are series-connected with the source of one cell used as the drain of the adjacent one, thereby forming a NAND configuration with a series of memory cells. Select transistors are placed at both ends of each NAND series. The source or drain of one select transistor is connected to a bit line through a bit line contact, while the source or drain of the other select transistor is connected to a source line through a source line contact.
In manufacturing such a NAND type flash memory, a gate preformation process may be used. This process involves forming a gate oxide over the entire surface of a silicon substrate (including the memory cell area and the peripheral circuit area), depositing a polysilicon film which will serve as floating gates of memory cells (cell transistors), patterning the deposited polysilicon film to form floating gate electrodes, and forming an insulating film for trench type device isolation regions to self-align to the floating gate electrodes.
At least part of a number of peripheral transistors that make up peripheral circuits of memory cells (for example, the select transistors) may be formed into the stacked gate structure which, like the memory cells, comprises a charge storage layer and a control gate layer. In this case, the gates of transistors of the same gate structure in the memory cell area and the peripheral circuit area can be processed under the same etching conditions, allowing the processing steps to be reduced and the processing processes to be made common to each other.
FIGS. 18A, 18B and 18C are sectional views, at a stage of manufacture, of a conventional NAND type flash memory. More specifically, FIGS. 18A and 18B are sectional views of the stacked gate structure of memory cells in the direction of gate width W (in the direction of word lines) and in the direction of gate length L, respectively, and FIG. 18B is a sectional view of a peripheral transistor in the direction of gate length L. FIGS. 19A, 19B and 19C through FIGS. 22A, 22B and 22C are sectional views, at subsequent stages of manufacture, of the same portions of the conventional NAND type flash memory as in FIGS. 18A, 18B and 18C, respectively.
First, as shown in FIGS. 18A, 18B and 18C, a first insulating film 11 is formed over the entire surface of a semiconductor substrate (Si substrate) 10. A first layer 13a (lower layer) of polysilicon for floating gate electrode is then formed on the first insulating film 11.
Next, device isolation trenches are formed to self-align to the floating gate electrodes 13a and an insulating film is deposited to fill the device isolation trenches. After that, the deposited insulating film is smoothed until the surface of the first floating gate electrode layer 13a is exposed, thereby forming device isolation regions 30. In this case, the top of the device isolation regions 30 is at a level above the Si substrate surface. That is, a step exists between the top of the device isolation region 30 and the Si substrate surface.
Next, a floating gate electrode layer 13b as a second layer consisting of polysilicon is formed over the entire surface and then patterned by means of lithographic and etching techniques. In this case, the second floating gate electrode layer 13b is stacked on the first floating gate electrode layer 13a and patterned to overlap the device isolation regions 30.
Next, a second insulating film 12 is formed over the entire surface of the substrate. A control gate electrode layer 14 is formed on the second insulating film 12 and then formed on top with a gate masking material layer 31.
Next, as shown in FIGS. 19A, 19B and 19C, the gate masking material layer 31 is patterned to form a gate masking pattern 31.
Next, as shown in FIGS. 20A, 20B and 20C, the control gate electrode layer 14 is etched using the gate masking pattern 31 as a mask.
Next, as shown in FIGS. 21A, 21B and 21C, the second insulating film 12 is etched using the gate masking pattern 31 as a mask.
Next, as shown in FIGS. 22A, 22B and 22C, the second floating gate electrode layer 13b and the first floating gate electrode layer 13a are etched using the gate masking pattern 31 as a mask. Thereby, the stacked gate structure is obtained in which the floating gate electrode 13 in the form of two layers and the control gate electrode 14 are stacked. In this stage, a two-layer gate structure which is the same as that shown in FIG. 18A is left below the word lines in the direction of gate width W in the memory cell area. Also, in this state, the top of the device isolation regions 30 is above the Si substrate surface level. That is, a step is formed between the top of the device isolation region 30 and the Si substrate surface.
After that, the stacked gates are covered with a capping material and then an interlayer insulating film is formed over the entire substrate of the substrate. Next, contact windows are formed in the interlayer insulating film and an interconnect layer is then formed.
In forming the interlayer insulating film, a BPSG film in which impurities, such as boron or phosphorus, are mixed into a silicon dioxide film to increase melting performance is deposited and then planarized by means of CMP. After that, contact windows are formed in the interlayer insulating film by dry etching. In this case, unless the etch selectivity between the capping material and the interlayer insulating film is high, the capping material on the gates will also be etched to reduce the thickness or removed thoroughly to expose the gates. Then, in filling the contact material into the contact windows, failures may occur in which the gates and the contact material are short-circuited. Thus, as the capping material use is made of a silicon nitride-based film which has relatively high etch selectivity to the silicon dioxide-based interlayer insulating film.
In the structure of FIGS. 22A-22C realized by the gate preformation process, the device isolation insulating film 30 is formed to self-align to the sidewall of the floating gate electrodes 13a and its top is above the Si substrate surface level. That is, the active regions in the Si substrate are surrounded by the device isolation insulating film 30 whose top is above the surface level of the active regions.
However, it has become clear that such a structure as described above causes various problems as device dimensions are scaled down.
In many cases, as a contact window etching stopper a silicon nitride film is deposited on the substrate surface so as to prevent contact windows from being formed too deep in those portions of the interlayer insulating film formed over the entire surface after the formation of stacked gates which are located over the source/drain regions of memory cells. That is, the etching of the interlayer insulating film stops at this silicon nitride film. The silicon nitride film is then etched in a short time under silicon nitride etching conditions.
However, as the source/drain regions of memory cells are scaled down, it becomes very difficult to form openings in the silicon nitride film formed on the surface of source/drain active regions which are surrounded by the device isolation regions to form trenches, since the silicon nitride film is buried on the surface of source/drain active regions. Even though it is not so difficult, a contact barrier film (SiN) is formed on sidewalls of the device isolation regions with the result that the thickness of the silicon nitride film on sidewalls increases, resulting in failure to remove the sidewall silicon nitride film at the time of formation of contact windows (the silicon nitride film is left as sidewall spacers). Thus, the contact area is reduced and the contact resistance is increased.
As a measure for this problem, in Japanese Patent Application No. 2000-245029 assigned to the same assignee as this application, a proposal has been made for a structure which allows the device isolation insulating film to be reduced in step height by etching the device isolation insulating film and the gate insulating film on the substrate surface after the formation of the floating gate electrodes.
According to such a structure, it becomes possible to minimize the problem that the contact barrier film is formed on the sidewall of the device isolation insulating film when the contact windows are formed on the source/drain regions of memory cells by means of RIE or the silicon nitride film is buried on the top of the source/drain active regions.
However, even with the structure in which the step height of the device isolation insulating film is reduced by etching the device isolation insulating film and the gate insulating film on the substrate surface after the formation of the floating gate electrodes, it has become clear that a problem still remains.
First, in etching the device isolation insulating film by RIE after the formation of the floating gate electrode, the gate insulating film on the source/drain regions would also etched away, causing the Si substrate to undergo etching.
Normally, use is made of etching conditions in which the etch rate of the device isolation insulating film (silicon oxide film) is high, whereas the etch rate of the Si substrate is low; nevertheless, the Si substrate would be subjected to etching to some extent and the substrate surface level would be lowered.
As a result, the depth of the source/drain regions equivalently increases by the amount that the substrate surface level is lowered, leading to the short-channel effect and performance degradation of the memory cells and transistors. This is important in view of a requirement of making the depth of the source/drain regions of memory cells and transistors from the gate oxide surface as small as possible as device dimensions are scaled down.
Furthermore, when the Si substrate is subjected to etching under etching conditions for the device isolation insulating film (silicon oxide film), an element, such as carbon, is driven as impurities into the Si substrate or the Si substrate is damaged by etching plasma. This will result in problems of degradation in the quality of a post-oxide film to be formed later, the occurrence of junction leakage current in source/drain diffused regions, and the occurrence of defective crystal.
When the active regions (device regions) in the Si substrate are surrounded by higher device isolation insulating film, it becomes impossible to etch away the gate material layer on the sidewall of the device isolation insulating film. That is, the gate material is left.
In this case, as the ratio between the opening of the portion surrounded by the device isolation insulating film and the depth to the device region (active region aspect ratio) increases, it becomes more difficult for an etching gas to flow into that portion and hence the gate material becomes more easy to be left.
The remaining gate material would cause gate electrodes to be short-circuited. In many cases, etching under conditions that the gate oxide film is small in thickness and a reduction in the thickness of the gate oxide film should be minimized during etching of the gate layer makes it easier for the gate material to be left.
To scale down the dimensions of memory cells, a structure of memory cells and peripheral transistors has been proposed in Japanese Patent Application No. 2000-291910 assigned to the same assignee as this application. According to this structure, a floating gate electrode of one layer structure (first electrode layer) is formed and a device isolation region is formed to self-align to the first electrode layer.
FIG. 23 shows, in sectional view, the memory cell area and the peripheral circuit area of a semiconductor device disclosed in Japanese Patent Application No. 2000-291910.
The memory cell area comprises a semiconductor substrate 11, device isolation regions 15 that isolate device regions 10 in the substrate, a first electrode layer (floating gate electrodes) 13 formed over the device regions 10 with a first insulating film 12 interposed therebetween, a second insulating film 16 formed on the first electrode layer 13 and the device isolation regions 15, and a second electrode layer (control gate electrode) 18 formed on the second insulating film 16. The top of the device isolation regions 15 is below the surface level of the first electrode layer 13.
The method of manufacture of the semiconductor device of FIG. 23 will be described next.
First, the first insulating film 51 is formed over the surface of the substrate 50. The floating gate electrodes 53 are formed on the first insulating film 51. The device isolation trenches are formed in the substrate to self-align to the floating gate electrodes 53. An insulating film is deposited over the entire surface of the substrate to fill the device isolation trenches. The insulating film is planarized until the top of the floating gate electrodes 53 is exposed, thereby forming the device isolation regions 60.
Next, the upper portion of each device isolation region is removed until the top of the device isolation region 30 in the memory cell area is located below the top of the floating gate electrodes 53. After that, the second insulating film (a composite insulating film including a silicon nitride film is desired; for example, an ONO film) 52 is formed over the entire surface of the substrate. A portion of the second insulating film 52 which is located over the device region in the peripheral circuit area is removed by means of lithographic and etching techniques. As a result, a portion of the surface of the floating gate electrode 53 is exposed to form an opening 61. Next, the control gate electrode layer 54 is formed over the entire surface of the substrate. The control gate electrode layer 54 and the second insulating film 52 are patterned. The control gate electrode layer 54 is lower in resistivity than the floating gate electrode 53 and preferably made of a refractory metal or refractory metal silicide.
Next, a third insulating film 62 is formed over the entire surface of the substrate. Contact holes 63 are formed in portions of the third insulating film 62 which are located above the device isolation regions 60 and interconnect lines 64 are then formed.
As a result, in the memory cell area, the interconnect line 64 and the second electrode layer 54 are connected together and, in the peripheral circuit area, the interconnect line 64 and the floating gate electrode 53 are connected through the second electrode layer 54.
Even in the structure which is realized by the gate preformation process, the device isolation insulating film 60 is formed to self-align to the floating gate electrodes 53 and the top thereof is located at a level above the Si substrate surface. That is, each active region in the Si substrate is surrounded by the higher device isolation insulating film 60.
In the above-described structure, the lower gate layer (corresponding to the floating gate layer in the memory cell area) of the peripheral transistor is in contact with the sidewall of the device isolation insulating film 60 which is thick in comparison with that in the conventional structure. In etching the lower gate layer, a portion of the gate material is left unetched on the sidewall of the device isolation insulating film as in the memory cell area, causing gate electrodes to be short-circuited.
In optimizing the etching condition at a certain active region aspect ratio, the optimum condition may be found. However, in the peripheral circuit area, unlike the memory cell area, it is very difficult to set the optimum condition because various active region aspect ratios are involved. In many cases, the peripheral transistor has a low-voltage-operated logic circuit connected to it. Since the gate insulating film of the peripheral transistor is normally small in thickness, the gate material is more prone to be left unetched. In particular, problems are involved in processing the stacked gates of memory cells and peripheral transistors at the same time.
As described above, the conventional semiconductor devices have a problem of gate electrodes being short-circuited because a portion of the gate material is left unetched on the sidewall of the device isolation insulating film whose top is above the surface level of active regions in the Si substrate.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a plurality of trench type device isolation regions formed in a semiconductor substrate; a plurality of semiconductor active regions electrically isolated by the device isolation regions; a first electrode layer formed to self-align to the semiconductor active regions; and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the device isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the semiconductor active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the semiconductor active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.